// *********************************************************************************
// Project Name : zkx2024
// Author       : Jlan
// Email        : 15533610762@163.com
// Create Time  : 2024-04-12
// File Name    : interface.sv
// Module Name  :
// Called By    :
// Abstract     :all inter module communication.
//
// 
// *********************************************************************************
// Modification History:
// Date         By              Version                 Change Description
// -----------------------------------------------------------------------
// 2024-04-12    Macro           1.0                     Original
// 2024-04-15    jlan            1.1                     interface done!  
// 2024-04-22    xfsong          1.2                     add st_imc_bus  
// *********************************************************************************


// *********************************************************************************
//wr_bus
interface wr_bus();
    logic   [0:0]       WR_SOP;
    logic   [0:0]       WR_EOP;
    logic   [0:0]       WR_VLD;
    logic   [35:0]      WR_DATA;

    modport master(
    output  WR_SOP,
    output  WR_EOP,
    output  WR_VLD,
    output  WR_DATA
    );

    modport slave(
    input   WR_SOP,
    input   WR_EOP,
    input   WR_VLD,
    input   WR_DATA
    );
endinterface
// *********************************************************************************

// *********************************************************************************
//rd_bus
interface rd_bus();
    logic   [0:0]       RD_SOP;
    logic   [0:0]       RD_EOP;
    logic   [0:0]       RD_VLD;
    logic   [35:0]      RD_DATA;

    modport master(
    output  RD_SOP,
    output  RD_EOP,
    output  RD_VLD,
    output  RD_DATA
    );

    modport slave(
    input   RD_SOP,
    input   RD_EOP,
    input   RD_VLD,
    input   RD_DATA
    );
endinterface
// *********************************************************************************


// *********************************************************************************
//raddr_st_bus


interface raddr_st_bus();
    logic [7:0]     READY;
    logic [0:0]     PRIORITY_JMP;
    logic [0:0]     RD_VLD;
    logic [17:0]    DATA_ADDR;
    logic [9:0]     DATA_SIZE;
    logic [1:0]     RD_STATE;
    logic [0:0]     RD_STATE_VLD;
    logic [0:0]     FLUSH_START;
    logic [0:0]     FLUSH_END;

    modport raddr (
    output  READY,
    input   PRIORITY_JMP,
    input   RD_VLD,
    input   DATA_ADDR,
    input   DATA_SIZE,
    output  RD_STATE,
    output  RD_STATE_VLD,
    input   FLUSH_START,
    output  FLUSH_END
    );

    modport st (
    input   READY,
    output  PRIORITY_JMP,
    output  RD_VLD,
    output  DATA_ADDR,
    output  DATA_SIZE,
    input   RD_STATE,
    input   RD_STATE_VLD,
    output  FLUSH_START,
    input   FLUSH_END
    );

endinterface
// *********************************************************************************

// *********************************************************************************
//cc_st_bus


interface cc_st_bus();
    logic [0:0]     SRAM_SHARE_VLD;
    logic [3:0]     SRAM_SHARE;
    logic [0:0]     SRAM_RELEASE_VLD;
    logic [3:0]     SRAM_RELEASE;
    logic [0:0]     ST_REQ;
    logic [31:0]    ST_REQ_DATA;
    logic [0:0]     ST_VLD;
    logic [31:0]    ST_VLD_DATA;
    logic [0:0]     PORT_READ;
    logic [7:0]     FULL;
    logic [7:0]     EMPTY;
    logic [0:0]     DATA_STATUS0;
    logic [2:0]     DATA_PRI0;
    logic [10:0]    DATA_SIZE0;
    logic [0:0]     WR_SOP0;
    logic [0:0]     WR_EOP0;
    logic [0:0]     WR_VLD0;
    logic [35:0]    WR_DATA0;
    logic [0:0]     DATA_STATUS1;
    logic [2:0]     DATA_PRI1;
    logic [10:0]    DATA_SIZE1;
    logic [0:0]     WR_SOP1;
    logic [0:0]     WR_EOP1;
    logic [0:0]     WR_VLD1;
    logic [35:0]    WR_DATA1;
    logic [0:0]     DATA_STATUS2;
    logic [2:0]     DATA_PRI2;
    logic [10:0]    DATA_SIZE2;
    logic [0:0]     WR_SOP2;
    logic [0:0]     WR_EOP2;
    logic [0:0]     WR_VLD2;
    logic [35:0]    WR_DATA2;
    logic [0:0]     DATA_STATUS3;
    logic [2:0]     DATA_PRI3;
    logic [10:0]    DATA_SIZE3;
    logic [0:0]     WR_SOP3;
    logic [0:0]     WR_EOP3;
    logic [0:0]     WR_VLD3;
    logic [35:0]    WR_DATA3;
    
    modport cc (
    output  SRAM_SHARE_VLD,
    output  SRAM_SHARE,
    input   SRAM_RELEASE_VLD,
    input   SRAM_RELEASE,
    output  ST_REQ,
    output  ST_REQ_DATA,
    input   ST_VLD,
    input   ST_VLD_DATA,
    input   PORT_READ,
    input   FULL,
    input   EMPTY,
    output  DATA_STATUS0,
    output  DATA_PRI0,
    output  DATA_SIZE0,
    output  WR_SOP0,
    output  WR_EOP0,
    output  WR_VLD0,
    output  WR_DATA0,
    output  DATA_STATUS1,
    output  DATA_PRI1,
    output  DATA_SIZE1,
    output  WR_SOP1,
    output  WR_EOP1,
    output  WR_VLD1,
    output  WR_DATA1,
    output  DATA_STATUS2,
    output  DATA_PRI2,
    output  DATA_SIZE2,
    output  WR_SOP2,
    output  WR_EOP2,
    output  WR_VLD2,
    output  WR_DATA2,
    output  DATA_STATUS3,
    output  DATA_PRI3,
    output  DATA_SIZE3,
    output  WR_SOP3,
    output  WR_EOP3,
    output  WR_VLD3,
    output  WR_DATA3
    );

    modport st (
    input   SRAM_SHARE_VLD,
    input   SRAM_SHARE,
    output  SRAM_RELEASE_VLD,
    output  SRAM_RELEASE,
    input   ST_REQ,
    input   ST_REQ_DATA,
    output  ST_VLD,
    output  ST_VLD_DATA,
    output  PORT_READ,
    output  FULL,
    output  EMPTY,
    input   DATA_STATUS0,
    input   DATA_PRI0,
    input   DATA_SIZE0,
    input   WR_SOP0,
    input   WR_EOP0,
    input   WR_VLD0,
    input   WR_DATA0,
    input   DATA_STATUS1,
    input   DATA_PRI1,
    input   DATA_SIZE1,
    input   WR_SOP1,
    input   WR_EOP1,
    input   WR_VLD1,
    input   WR_DATA1,
    input   DATA_STATUS2,
    input   DATA_PRI2,
    input   DATA_SIZE2,
    input   WR_SOP2,
    input   WR_EOP2,
    input   WR_VLD2,
    input   WR_DATA2,
    input   DATA_STATUS3,
    input   DATA_PRI3,
    input   DATA_SIZE3,
    input   WR_SOP3,
    input   WR_EOP3,
    input   WR_VLD3,
    input   WR_DATA3
    );
     
endinterface
// *********************************************************************************

// *********************************************************************************
//wraddr_srammux_bus

interface wraddr_srammux_bus();
    logic [0:0]     WR_EN;
    logic [12:0]    WR_ADDR;
    logic [35:0]    WR_DATA;
    logic [4:0]     WR_SRAM_NUM;

    modport wraddr(
    output  WR_EN,
    output  WR_ADDR,
    output  WR_DATA,
    output  WR_SRAM_NUM
    );

    modport srammux(
    input   WR_EN,
    input   WR_ADDR,
    input   WR_DATA,
    input   WR_SRAM_NUM
    );

endinterface
// *********************************************************************************

// *********************************************************************************
//wraddr_st_bus

interface wraddr_st_bus();
    logic [0:0]     SOP;
    logic [0:0]     VLD;
    logic [35:0]    DATA;
    logic [17:0]    ADDR;
    logic [0:0]     EOP;

    modport wraddr(
    input   SOP,
    input   VLD,
    input   DATA,
    input   ADDR,
    input   EOP
    );

    modport st(
    output  SOP,
    output  VLD,
    output  DATA,
    output  ADDR,
    output  EOP
    );

endinterface
// *********************************************************************************

// *********************************************************************************
//srammux_sram_bus

interface srammux_sram_bus();
    logic [35:0]    W_DATA;
    logic [12:0]    W_ADDR;
    logic [35:0]    R_DATA;
    logic [12:0]    R_ADDR;
    logic [0:0]     WR;
    logic [0:0]     RD;
    logic [0:0]     CS;

    modport srammux(
    input   R_DATA,
    output  W_DATA,
    output  W_ADDR,
    output  R_ADDR,
    output  WR,
    output  RD,
    output  CS
    );

    modport sram(
    output  R_DATA,
    input   W_DATA,
    input   W_ADDR,
    input   R_ADDR,
    input   WR,
    input   RD,
    input   CS
    );

endinterface
// *********************************************************************************
// *********************************************************************************
//rdaddr_srammux_bus
interface rdaddr_srammux_bus();
    logic [0:0]  RD_EN;
    logic [17:0] RD_ADDR;
    logic [35:0] RD_DATA;
    logic [0:0]  RD_DATA_VLD;

    modport raddr(
    input   RD_DATA,
    input   RD_DATA_VLD,
    output  RD_EN,
    output  RD_ADDR
    );

    modport srammux(
    output  RD_DATA,
    output  RD_DATA_VLD,
    input   RD_EN,
    input   RD_ADDR
    );

endinterface

// *********************************************************************************
// *********************************************************************************
//de_cc_bus
interface de_cc_bus();
    logic [2:0]  VLD;
    logic [0:0]  REQ;
    logic [3:0]  DATA_DEST;
    logic [2:0]  DATA_PRIO;
    logic [10:0] DATA_SIZE;
    logic [35:0] WR_DATA;
    logic [0:0]  WR_SOP;
    logic [0:0]  WR_EOP;
    logic [0:0]  WR_VLD;

    modport de(
    output  REQ,
    input   VLD,
    output  DATA_DEST,
    output  DATA_PRIO,
    output  DATA_SIZE,
    output  WR_DATA,
    output  WR_SOP,
    output  WR_EOP,
    output  WR_VLD
    );

    modport cc(
    input   REQ,
    output  VLD,
    input   DATA_DEST,
    input   DATA_PRIO,
    input   DATA_SIZE,
    input   WR_DATA,
    input   WR_SOP,
    input   WR_EOP,
    input   WR_VLD
    );

endinterface

// *********************************************************************************


// *********************************************************************************
//st_fifo_bus

interface st_fifo_bus(
    input   logic   CLK,
    input   logic   RST_N
);

parameter       FIFO_WIDTH  =   4;

    logic   [0:0]               WR_EN;
    logic   [FIFO_WIDTH-1:0]    WR_DATA;
    logic   [0:0]               RD_EN;
    logic   [0:0]               CLEAR;
    logic   [0:0]               FLUSH;
    logic   [FIFO_WIDTH-1:0]    RD_DATA;
    logic   [0:0]               FULL;
    logic   [0:0]               EMPTY;

    modport st(
        input  CLK,
        input  RST_N,
        output  WR_EN,
        output  WR_DATA,
        output  RD_EN,
        output  CLEAR,
        output  FLUSH,
        input   RD_DATA,
        input   FULL,
        input   EMPTY
    );

    modport fifo(
        input   CLK,
        input   RST_N,
        input   WR_EN,
        input   WR_DATA,
        input   RD_EN,
        input   CLEAR,
        input   FLUSH,
        output  RD_DATA,
        output  FULL,
        output  EMPTY
    );
endinterface
// *********************************************************************************

// *********************************************************************************
//st_tx_dd_bus
interface st_tx_dd_bus();
    logic   [0:0]       WR_SOP;
    logic   [0:0]       WR_EOP;
    logic   [0:0]       WR_VLD;
    logic   [31:0]      WR_DATA;

    modport master(
    output  WR_SOP,
    output  WR_EOP,
    output  WR_VLD,
    output  WR_DATA
    );

    modport slave(
    input   WR_SOP,
    input   WR_EOP,
    input   WR_VLD,
    input   WR_DATA
    );
endinterface

// *********************************************************************************

// *********************************************************************************
//rd_bus_error
interface rd_bus_error();
    logic   [0:0]       RD_SOP;
    logic   [0:0]       RD_EOP;
    logic   [0:0]       RD_VLD;
    logic   [31:0]      RD_DATA;
    logic   [0:0]       RD_ERROR;

    modport master(
    output  RD_SOP,
    output  RD_EOP,
    output  RD_VLD,
    output  RD_DATA,
    output  RD_ERROR
    );

    modport slave(
    input   RD_SOP,
    input   RD_EOP,
    input   RD_VLD,
    input   RD_DATA,
    input   RD_ERROR
    );
endinterface

// *********************************************************************************

// *********************************************************************************
//st_imc_bus  for 4 single datapath between st and cac
interface st_imc_bus();
    logic   [0:0]   WR_REQ;
    logic   [0:0]   WR_VLD;
    logic   [17:0]  WR_ADDR;
    logic   [0:0]   WR_DATA_VLD;
    logic   [29:0]  WR_DATA_VALUE;

    modport st(
    output   WR_REQ,
    input    WR_VLD,
    input    WR_ADDR,
    output   WR_DATA_VLD,
    output   WR_DATA_VALUE
    );

    modport imc(
    input    WR_REQ,
    output   WR_VLD,
    output   WR_ADDR,
    input    WR_DATA_VLD,
    input    WR_DATA_VALUE
    );

endinterface

// *********************************************************************************
// *********************************************************************************
//st_cac_bus   for 1 group datapath between st and imc
interface st_cac_bus();
    logic   [0:0]       RD_DATA_VLD;
    logic   [29:0]      RD_DATA_VALUE;
    logic   [3:0]       FULL;
    logic   [3:0]       EMPTY;
    logic   [0:0]       SRAM_VLD;
    logic   [3:0]       SRAM_SHARE;
    logic   [0:0]       SRAM_RELEASE_VLD;
    logic   [3:0]       SRAM_RELEASE;

    modport st  (
    output  RD_DATA_VLD,
    output  RD_DATA_VALUE,
    input   FULL,
    input   EMPTY,
    output  SRAM_VLD,
    output  SRAM_SHARE,
    output  SRAM_RELEASE_VLD,
    output  SRAM_RELEASE
    );

    modport cac (
    input   RD_DATA_VLD,
    input   RD_DATA_VALUE,
    output  FULL,
    output  EMPTY,
    input   SRAM_VLD,
    input   SRAM_SHARE,
    input   SRAM_RELEASE_VLD,
    input   SRAM_RELEASE
    );
endinterface

interface   sc_bus();
    logic   [0:0]   CLK;
    logic   [0:0]   RST_N;
    logic   [7:0] FULL_O_0;
    logic   [7:0] FULL_O_1;
    logic   [7:0] FULL_O_2;
    logic   [7:0] FULL_O_3;
    logic   [7:0] FULL_O_4;
    logic   [7:0] FULL_O_5;
    logic   [7:0] FULL_O_6;
    logic   [7:0] FULL_O_7;
    logic   [7:0] FULL_O_8;
    logic   [7:0] FULL_O_9;
    logic   [7:0] FULL_O_10;
    logic   [7:0] FULL_O_11;
    logic   [7:0] FULL_O_12;
    logic   [7:0] FULL_O_13;
    logic   [7:0] FULL_O_14;
    logic   [7:0] FULL_O_15;
    logic    WR_SOP_I_0;
    logic    WR_SOP_I_1;
    logic    WR_SOP_I_2;
    logic    WR_SOP_I_3;
    logic    WR_SOP_I_4;
    logic    WR_SOP_I_5;
    logic    WR_SOP_I_6;
    logic    WR_SOP_I_7;
    logic    WR_SOP_I_8;
    logic    WR_SOP_I_9;
    logic    WR_SOP_I_10;
    logic    WR_SOP_I_11;
    logic    WR_SOP_I_12;
    logic    WR_SOP_I_13;
    logic    WR_SOP_I_14;
    logic    WR_SOP_I_15;
    logic    WR_EOP_I_0;
    logic    WR_EOP_I_1;
    logic    WR_EOP_I_2;
    logic    WR_EOP_I_3;
    logic    WR_EOP_I_4;
    logic    WR_EOP_I_5;
    logic    WR_EOP_I_6;
    logic    WR_EOP_I_7;
    logic    WR_EOP_I_8;
    logic    WR_EOP_I_9;
    logic    WR_EOP_I_10;
    logic    WR_EOP_I_11;
    logic    WR_EOP_I_12;
    logic    WR_EOP_I_13;
    logic    WR_EOP_I_14;
    logic    WR_EOP_I_15;
    logic    WR_VLD_I_0;
    logic    WR_VLD_I_1;
    logic    WR_VLD_I_2;
    logic    WR_VLD_I_3;
    logic    WR_VLD_I_4;
    logic    WR_VLD_I_5;
    logic    WR_VLD_I_6;
    logic    WR_VLD_I_7;
    logic    WR_VLD_I_8;
    logic    WR_VLD_I_9;
    logic    WR_VLD_I_10;
    logic    WR_VLD_I_11;
    logic    WR_VLD_I_12;
    logic    WR_VLD_I_13;
    logic    WR_VLD_I_14;
    logic    WR_VLD_I_15;
    logic    [31:0] WR_DATA_I_0;
    logic    [31:0] WR_DATA_I_1;
    logic    [31:0] WR_DATA_I_2;
    logic    [31:0] WR_DATA_I_3;
    logic    [31:0] WR_DATA_I_4;
    logic    [31:0] WR_DATA_I_5;
    logic    [31:0] WR_DATA_I_6;
    logic    [31:0] WR_DATA_I_7;
    logic    [31:0] WR_DATA_I_8;
    logic    [31:0] WR_DATA_I_9;
    logic    [31:0] WR_DATA_I_10;
    logic    [31:0] WR_DATA_I_11;
    logic    [31:0] WR_DATA_I_12;
    logic    [31:0] WR_DATA_I_13;
    logic    [31:0] WR_DATA_I_14;
    logic    [31:0] WR_DATA_I_15;
//    rd_bus.master rd_out_0,
//    rd_bus.master rd_out_1,
//    rd_bus.master rd_out_2,
//    rd_bus.master rd_out_3,
//    rd_bus.master rd_out_4,
//    rd_bus.master rd_out_5,
//    rd_bus.master rd_out_6,
//    rd_bus.master rd_out_7,
//    rd_bus.master rd_out_8,
//    rd_bus.master rd_out_9,
//    rd_bus.master rd_out_10,
//    rd_bus.master rd_out_11,
//    rd_bus.master rd_out_12,
//    rd_bus.master rd_out_13,
//    rd_bus.master rd_out_14,
    logic   [0:0]       RD_SOP0;
    logic   [0:0]       RD_EOP0;
    logic   [0:0]       RD_VLD0;
    logic   [31:0]      RD_DATA0;
    logic   [0:0]       RD_ERROR0;
    logic   [0:0]       RD_SOP1;
    logic   [0:0]       RD_EOP1;
    logic   [0:0]       RD_VLD1;
    logic   [31:0]      RD_DATA1;
    logic   [0:0]       RD_ERROR1;
    logic   [0:0]       RD_SOP2;
    logic   [0:0]       RD_EOP2;
    logic   [0:0]       RD_VLD2;
    logic   [31:0]      RD_DATA2;
    logic   [0:0]       RD_ERROR2;
    logic   [0:0]       RD_SOP3;
    logic   [0:0]       RD_EOP3;
    logic   [0:0]       RD_VLD3;
    logic   [31:0]      RD_DATA3;
    logic   [0:0]       RD_ERROR3;
    logic   [0:0]       RD_SOP4;
    logic   [0:0]       RD_EOP4;
    logic   [0:0]       RD_VLD4;
    logic   [31:0]      RD_DATA4;
    logic   [0:0]       RD_ERROR4;
    logic   [0:0]       RD_SOP5;
    logic   [0:0]       RD_EOP5;
    logic   [0:0]       RD_VLD5;
    logic   [31:0]      RD_DATA5;
    logic   [0:0]       RD_ERROR5;
    logic   [0:0]       RD_SOP6;
    logic   [0:0]       RD_EOP6;
    logic   [0:0]       RD_VLD6;
    logic   [31:0]      RD_DATA6;
    logic   [0:0]       RD_ERROR6;
    logic   [0:0]       RD_SOP7;
    logic   [0:0]       RD_EOP7;
    logic   [0:0]       RD_VLD7;
    logic   [31:0]      RD_DATA7;
    logic   [0:0]       RD_ERROR7;
    logic   [0:0]       RD_SOP8;
    logic   [0:0]       RD_EOP8;
    logic   [0:0]       RD_VLD8;
    logic   [31:0]      RD_DATA8;
    logic   [0:0]       RD_ERROR8;
    logic   [0:0]       RD_SOP9;
    logic   [0:0]       RD_EOP9;
    logic   [0:0]       RD_VLD9;
    logic   [31:0]      RD_DATA9;
    logic   [0:0]       RD_ERROR9;
    logic   [0:0]       RD_SOP10;
    logic   [0:0]       RD_EOP10;
    logic   [0:0]       RD_VLD10;
    logic   [31:0]      RD_DATA10;
    logic   [0:0]       RD_ERROR10;
    logic   [0:0]       RD_SOP11;
    logic   [0:0]       RD_EOP11;
    logic   [0:0]       RD_VLD11;
    logic   [31:0]      RD_DATA11;
    logic   [0:0]       RD_ERROR11;
    logic   [0:0]       RD_SOP12;
    logic   [0:0]       RD_EOP12;
    logic   [0:0]       RD_VLD12;
    logic   [31:0]      RD_DATA12;
    logic   [0:0]       RD_ERROR12;
    logic   [0:0]       RD_SOP13;
    logic   [0:0]       RD_EOP13;
    logic   [0:0]       RD_VLD13;
    logic   [31:0]      RD_DATA13;
    logic   [0:0]       RD_ERROR13;
    logic   [0:0]       RD_SOP14;
    logic   [0:0]       RD_EOP14;
    logic   [0:0]       RD_VLD14;
    logic   [31:0]      RD_DATA14;
    logic   [0:0]       RD_ERROR14;
    logic   [0:0]       RD_SOP15;
    logic   [0:0]       RD_EOP15;
    logic   [0:0]       RD_VLD15;
    logic   [31:0]      RD_DATA15;
    logic   [0:0]       RD_ERROR15;
//    rd_bus.master rd_out_15,
    logic [7:0] READY_0;
    logic [7:0] READY_1;
    logic [7:0] READY_2;
    logic [7:0] READY_3;
    logic [7:0] READY_4;
    logic [7:0] READY_5;
    logic [7:0] READY_6;
    logic [7:0] READY_7;
    logic [7:0] READY_8;
    logic [7:0] READY_9;
    logic [7:0] READY_10;
    logic [7:0] READY_11;
    logic [7:0] READY_12;
    logic [7:0] READY_13;
    logic [7:0] READY_14;
    logic [7:0] READY_15;
    logic QOS_SEL_I_0;
    logic QOS_SEL_I_1;
    logic QOS_SEL_I_2;
    logic QOS_SEL_I_3;
    logic QOS_SEL_I_4;
    logic QOS_SEL_I_5;
    logic QOS_SEL_I_6;
    logic QOS_SEL_I_7;
    logic QOS_SEL_I_8;
    logic QOS_SEL_I_9;
    logic QOS_SEL_I_10;
    logic QOS_SEL_I_11;
    logic QOS_SEL_I_12;
    logic QOS_SEL_I_13;
    logic QOS_SEL_I_14;
    logic QOS_SEL_I_15;

endinterface
// *********************************************************************************

